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1 ae1e fujitsu semiconductor data sheet memory cmos 8 x 256k x 32 bit double data rate fcram tm MB81N643289-50/-60 cmos 8-bank x 262,144-word x 32 bit fast cycle random access memory (fcram) with double data rate n description the fujitsu MB81N643289 is a cmos fast cycle random access memory (fcram) containing 67,108,864 memory cells accessible in an 32-bit format. the MB81N643289 features a fully synchronous operation referenced to clock edge whereby all operations are synchronized at a clock input which enables high performance and simple user interface coexistence. the MB81N643289 is designed to reduce the complexity of using a standard dynamic ram (dram) which requires many control signal timing constraints. the MB81N643289 uses double data rate (ddr) where data bandwidth is twice of fast speed compared with regular sdrams. the MB81N643289 is designed using fujitsu advanced fcram core technology. the MB81N643289 is ideally suited for digital visual system, high performance graphic adapters, hardware accelerators, buffers, and other applications where large memory density and high effective bandwidth are required and where a simple interface is needed. the MB81N643289 adopts new i/o interface circuitry, 2.5 v cmos source termination i/o interface, which is capable of extremely fast data transfer of quality under point to point bus environment. n product line notice : fcram is a trademark of fujitsu limited, japan. parameter MB81N643289 -50 -60 clock frequency cl = 3 200 mhz max 167 mhz max cl = 2 133 mhz max 111 mhz max burst mode cycle time cl = 3 2.5 ns min 3.0 ns min cl = 2 3.75 ns min 4.5 ns min random address cycle time 30 ns min 36 ns min dqs access time from clock 0.1*t ck + 0.2 ns max 0.1*t ck + 0.2 ns max operating current 450 ma max 385 ma max power down current 35 ma max
2 MB81N643289-50/-60 preliminary (ae1e) n features n pac k ag e ? byte write control by dm 0 to dm 3 ? page close power down mode ? distributed auto-refresh cycle in 8 m s ? 2.5 v cmos source termination i/o for all signals ?v dd : +2.5v supply 0.2v tolerance ?v ddq : +2.5v supply 0.2v tolerance ? double data rate ? bi-directional data strobe signal ? eight bank operation ? burst read/write operation ? programmable, burst length, and cas latency ? write latency (write command to data input) = cas latency -1 package and ordering information C 86-pin plastic (400 mil) tsop-ii, order as MB81N643289- fn plastic tsop(ii) package (fpt-86p-m01) (normal bend)
3 MB81N643289-50/-60 preliminary (ae1e) n pin assignments and descriptions 86-pin tsop(ii) (top view) 74 73 72 71 70 69 68 67 66 86 85 84 83 82 81 80 79 78 77 1 2 3 4 5 9 10 6 7 8 13 14 15 16 17 18 19 20 21 22 76 75 11 12 65 64 63 62 61 60 23 24 25 26 27 58 57 56 55 54 53 52 51 50 29 30 31 32 33 34 35 36 37 38 59 28 49 48 47 46 45 44 39 40 41 42 43 v dd dq 0 v ddq dq 1 dq 2 v ssq dq 3 dq 4 v ddq dq 5 dq 6 v ssq dq 7 dqs 0 v dd dm 0 we cas ras cs ba 2 ba 0 ba 1 a 10 /ac a 0 a 1 a 2 dm 2 v dd dqs 2 dq 16 v ssq dq 17 dq 18 v ddq dq 19 dq 20 v ssq dq 21 dq 22 v ddq dq 23 v dd v ss dq 15 v ssq dq 14 dq 13 v ddq dq 12 dq 11 v ssq dq 10 dq 9 v ddq dq 8 dqs 1 v ss dm 1 v ref clk clk pd a 9 a 8 a 7 a 6 a 5 a 4 a 3 dm 3 v ss dqs 3 dq 31 v ddq dq 30 dq 29 v ssq dq 28 dq 27 v ddq dq 26 dq 25 v ssq dq 24 v ss pin number symbol function 1, 3, 9, 15, 29, 35, 41, 43, 49, 55, 75, 81 v dd , v ddq supply voltage 6, 12, 32, 38, 44, 46, 52, 58, 72, 78, 84, 86 v ss , v ssq ground 2, 4, 5, 7, 8, 10, 11, 13, 31, 33, 34, 36, 37, 39, 40, 42, 45, 47, 48, 50, 51, 53, 54, 56, 74, 76, 77, 79, 80, 82, 83, 85 dq 0 to dq 31 data i/o ? byte 0 : dq 0 to dq 7 ? byte 1 : dq 8 to dq 15 ? byte 2 : dq 16 to dq 23 ? byte 3 : dq 24 to dq 31 14, 30, 57, 73 dqs 0 to dqs 3 data strobe ?dqs 0 : for dq 0 to dq 7 ?dqs 1 : for dq 8 to dq 15 ?dqs 2 : for dq 16 to dq 23 ?dqs 3 : for dq 24 to dq 31 16, 28, 59, 71 dm 0 to dm 3 input mask 17 we write enable 18 cas column address strobe 19 ras row address strobe 20 cs chip select 21, 22, 23 ba 2 , ba 1 , ba 0 bank select (bank address) 24 ac auto close enable 24, 25, 26, 27, 60, 61, 62, 63, 64, 65, 66 a 0 to a 10 address input ? row: a 0 to a 10 ? column: a 0 to a 6 67 pd power down 68 clk clock input 69 clk clock input 70 v ref input reference voltage
4 MB81N643289-50/-60 preliminary (ae1e) n block diagram fig. 1 C MB81N643289 block diagram clk clk a 0 to a 10 ba 0 ,ba 1 ,ba 2 dq 0 to dq 31 ras cas we cs bank-1 v dd clock buffer control signal latch mode register column address counter ras cas we dram core (2048 x 128 x 32) column address bank-0 i/o row address to each block v ref command decoder address buffer/ register i/o data buffer/ register & dqs genera- tor dm 0 to dm 3 v ss / v ssq bank-7 ac dqs 0 to dqs 3 32 enable v ddq , v ssq pd dll clock buffer 11 7 . . . . . . . . .
5 MB81N643289-50/-60 preliminary (ae1e) n function truth table note *1 command truth table note *2, and *3 notes: *1. v = valid, l = logic low, h = logic high, x = either l or h, hi-z = high impedance. *2. all commands are assumed to be valid state transitions. *3. all inputs for command are latched on the rising edge of clock(clk). *4. nop and desl commands have the same effect on the part. unless specifically noted, nop will represent both nop and desl command in later descriptions. *5. rd, rda, wr and wra commands should only be issued after the corresponding bank has been activated (actv command). refer to state diagram in page 18. *6. actv command should only be issued after corresponding bank has been page closed by pc or pca command. *7. either pc or pca command and mrs or emrs command are required after power up. *8. mrs or emrs command should only be issued after all banks have been page closed (pc or pca command), and dqs are in hi-z. refer to state diagram. *9. refer to mode register table. function notes symbol pd cs ras cas we ac ba 2-0 a 10 a 9 a 8-7 a 6-0 device deselect *4 desl h h x x x x x x x x x no operation *4 nop h l h h h x x x x x x reserved hl h h l x x xxxx read *5 rd h l h l h l v x x x v read with auto-close *5 rda h l h l h h v x x x v write *5wr hl h l l l v xxxv write with auto-close *5 wra h l h l l h v x x x v bank active (ras ) *6actvhl l h hx v vvvv page close single bank *7 pc h l l h l l v x x x v page close all banks *7 pca h l l h l h x x x x v mode register set/ extended mode register set *7,*8,*9 mrs/ emrs hl l l l l v lvvv
6 MB81N643289-50/-60 preliminary (ae1e) n function truth table (continued) dm truth table (effective during write mode) pd truth table notes:*10. the ref and self commands should only be issued after all banks have been precharged (pc or pca command). in case of self command, it should also be issued after the last read data have been appeared on dq. refer to state diagram. *11. pd must bring to low level together with ref command. *12. the pden command should only be issued after the last read data have been appeared on dq and after the l wpl is satisfied from last write data input. function command pd dm 0 dm 1 dm 2 dm 3 (n - 1) (n) data mask for dq 0 to dq 7 mask0 h x h x x x data mask for dq 8 to dq 15 mask1 h x x h x x data mask for dq 16 to dq 23 mask2 h x x x h x data mask for dq 24 to dq 31 mask3hxxxxh current state function notes command pd cs ras cas we ac ba 0-2 a 10-0 dq 0-31 (n-1) (n) idle auto-refresh *10 ref h h l l l h x x x idle self-refresh entry *10 *11 self hlll lhxxxhi-z self- refresh self-refresh continue l l x x x x x x x hi-z self- refresh self-refresh exit selfx lhlhhhxxxhi-z lhhxxxxxxhi-z idle power down entry *12 pden hllhhhxxxhi-z hlhxxxxxxhi-z power down power down continue l l x x x x x x x hi-z power down power down exit pdex lhlhhhxxxhi-z lhhxxxxxxhi-z
7 MB81N643289-50/-60 preliminary (ae1e) n function truth table (continued) operation command table (applicable to single bank) note *13 current state cs ras cas we address command function notes idle hxxx x desl nop lhhh x nop nop l h h l illegal *14 l h l h ba, ca, ac rd/rda illegal *15 l h l l ba, ca, ac wr/wra illegal *15 l l h h ba, ra actv bank active after l rcd l l h l ba, ac pc nop llhl ba, ac pca nop *14 l l l h x ref/self auto-refresh or self-refresh *16 llll mode mrs/emrs mode register / extended mode register set (idle after l rsc ) *16 bank active h x x x x desl nop lhhh x nop nop l h h l illegal l h l h ba, ca, ac rd/rda begin read; determine ac l h l l ba, ca, ac wr/wra begin write; determine ac l l h h ba, ra actv illegal *15 l l h l ba, ac pc page close l l h l ba, ac pca page close *14 lllh x ref/selfillegal llll mode mrs/emrsillegal
8 MB81N643289-50/-60 preliminary (ae1e) n function truth table (continued) operation command table (continued) current state cs ras cas we address command function notes read hxxx x desl nop (continue burst to end -> bank active) lhhh x nop nop (continue burst to end -> bank active) l h h l illegal l h l h ba, ca, ac rd/rda illegal l h l l ba, ca, ac wr/wra illegal l l h h ba, ra actv illegal *15 l l h l ba, ac pc illegal l l h l ba, ac pca illegal *14 lllh x ref/selfillegal llll mode mrs/emrsillegal write hxxx x desl nop (continue burst to end -> bank active) lhhh x nop nop (continue burst to end -> bank active) l h h l illegal l h l h ba, ca, ac rd/rda illegal l h l l ba, ca, ac wr/wra illegal l l h h ba, ra actv illegal *15 l l h l ba, ac pc illegal l l h l ba, ac pca illegal *14 lllh x ref/selfillegal llll mode mrs/emrsillegal
9 MB81N643289-50/-60 preliminary (ae1e) n function truth table (continued) operation command table (continued) current state cs ras cas we address command function notes read with auto-close hxxx x desl nop (continue burst to end -> bank idle) lhhh x nop nop (continue burst to end -> bank idle) l h h l illegal l h l h ba, ca, ac rd/rda illegal *17 l h l l ba, ca, ac wr/wra illegal *17 l l h h ba, ra actv illegal *15 l l h l ba, ac pc illegal *15 l l h l ba, ac pca illegal lllh x ref/selfillegal llll mode mrs/emrsillegal write with auto-close hxxx x desl nop (continue burst to end -> bank idle) lhhh x nop nop (continue burst to end -> bank idle) l h h l illegal l h l h ba, ca, ac rd/rda illegal *17 l h l l ba, ca, ac wr/wra illegal *17 l l h h ba, ra actv illegal *15 l l h l ba, ac pc illegal *15 l l h l ba, ac pca illegal lllh x ref/selfillegal llll mode mrs/emrsillegal
10 MB81N643289-50/-60 preliminary (ae1e) n function truth table (continued) operation command table (continued) current state cs ras cas we address command function notes page close h x x x x desl nop (idle after t pcl ) l h h h x nop nop (idle after t pcl ) l h h l illegal l h l h ba, ca, ac rd/rda illegal *15 l h l l ba, ca, ac wr/wra illegal *15 l l h h ba, ra actv illegal *15 l l h l ba, ac pc nop *15 llhl ba, ac pca nop *14 lllh x ref/selfillegal llll mode mrs/emrsillegal bank activating h x x x x desl nop (bank active after l rcd ) l h h h x nop nop (bank active after l rcd ) l h h l illegal l h l h ba, ca, ac rd/rda illegal *15 l h l l ba, ca, ac wr/wra illegal *15 l l h h ba, ra actv illegal *15 l l h l ba, ac pc illegal *15 l l h l ba, ac pca illegal lllh x ref/selfillegal llll mode mrs/emrsillegal
11 MB81N643289-50/-60 preliminary (ae1e) n function truth table (continued) operation command table (continued) current state cs ras cas we address command function notes write recovering h x x x x desl nop (bank active after l wrl ) l h h h x nop nop (bank active after l wrl ) l h h l illegal l h l h ba, ca, ac rd/rda illegal l h l l ba, ca, ac wr/wra new write; determine ac l l h h ba, ra actv illegal l l h l ba, ac pc illegal *15 l l h l ba, ac pca illegal lllh x ref/selfillegal llll mode mrs/emrsillegal write recovering with auto- close h x x x x desl nop (idle after l wal ) l h h h x nop nop (idle after l wal ) l h h l illegal l h l h ba, ca, ac rd/rda illegal *17 l h l l ba, ca, ac wr/wra illegal *17 l l h h ba, ra actv illegal *15 l l h l ba, ac pc illegal *15 l l h l ba, ac pca illegal lllh x ref/selfillegal llll mode mrs/emrsillegal refreshing h x x x x desl nop (idle after l refc ) l h h x x nop nop (idle after l refc ) lhlx x rd/rda/ wr/wra illegal llhx x actv/ pc/pca illegal lllx x ref/self/ mrs/emrs illegal
12 MB81N643289-50/-60 preliminary (ae1e) n function truth table (continued) operation command table (continued) abbreviations: ra = row address ba = bank address ca = column address ac = auto close notes:*13. all entries assume the pd was high during the proceeding clock cycle and the current clock cycle. *14. entry may affect other banks. *15. illegal to bank in specified state; entry may be legal in the bank specified by ba, depending on the state of that bank. *16. illegal if any bank is not idle. *17. entry may legal specified by ba if applicable ac specification are satisfied. current state cs ras cas we address command function notes mode register setting h x x x x desl nop (idle after l rsc ) l h h h x nop nop (idle after l rsc ) l h h l illegal lhlx x rd/rda/ wr/wra illegal llxx x actv/pc/pca/ ref/self/ mrs/emrs illegal
13 MB81N643289-50/-60 preliminary (ae1e) n function truth table (continued) command truth table for pd current state pd cs ras cas we address function notes (n-1) (n) self- refresh hxxxxx xinvalid l h h x x x x exit self-refresh (idle after l lock ) l h l h h h x exit self-refresh (idle after l lock ) lhlhhl xillegal lhlhlx xillegal l h l l x x x illegal l lxxxx xnop (maintain self-refresh) self- refresh recovery lxxxxx xinvalid h h h x x x x idle after l lock hhlhhh xidle after l lock h h l h h l x illegal h h l h l x x illegal h h l l x x x illegal hlxxxx xillegal power down hxxxxx xinvalid l h h x x x x exit power down (idle after t pde ) l h l h h h x exit power down (idle after t pde ) lhlhhl xillegal lhlhlx xillegal l h l l x x x illegal l lxxxx xnop (maintain power down mode)
14 MB81N643289-50/-60 preliminary (ae1e) n function truth table (continued) command truth table for pd (continued) current state pd cs ras cas we address function notes (n-1) (n) all banks idle hhxxxx xrefer to the command truth table. h l h x x x x power down entry *18 h l l h h h x power down entry *18 hllhhl xillegal h l l h l x x illegal hlllhx xillegal hllllh xself-refresh entry hlllll xillegal lxxxxx xinvalid bank activehhxxxx xrefer to the command truth table. hlxxxx xillegal lhxxxx xinvalid l lxxxx xinvalid
15 MB81N643289-50/-60 preliminary (ae1e) n function truth table (continued) command truth table for pd (continued) *18. pden and self command should only be issued after the last read data have been appeared on dq. *19. the clock suspend mode is not supported on this device and it is illegal if pd is brought to low during the burst read or write mode. current state pd cs ras cas we address function notes (n-1) (n) read, write, write page closing hhxxxx xrefer to the command truth table. hlxxxx xill egal *19 lhxxxx xinvalid l lxxxx xinvalid any state other than listed above lxxxxx xinvalid hhxxxx xrefer to the command truth table. hlxxxx xill egal refreshing hhxxxx xrefer to the command truth table. h l h x x x x illegal h l l h h h x illegal h l l h h l x illegal h l l h l x x illegal h l l l x x x illegal l lxxxx xinvalid lhxxxx xinvalid hhxxxx xrefer to the command truth table.
16 MB81N643289-50/-60 preliminary (ae1e) n state diagram minimum clock latency or delay time for single bank operation notes: *1. assume pca command does not affect any operation on the other banks. *2. assume no i/o conflict. *3. t ras must be satisfied. *4. assume all outputs are in high-z state. *5. assume all other banks are in idle state. illegal command second command (same bank) mrs actv rd rda wr wra pc pca ref self first command mrs l rsc l rsc l rsc l rsc l rsc l rsc actv l rcd *3 l rcd l rcdw *3 l rcdw t ras t ras rd l ccd * 3 l ccd * 2 l rwl *2, 3 l rwl *3 l rpl *3 l rpl rda *4, 5 l rda l rda *3 l rda *3 l rda *5 l rda *4, 5 l rda wr l wrl *3 l wrl l ccd *3 l ccd *3 l wpl *3 l wpl wra *5 l wal l wal *3 l wal *3 l wal *5 l wal *5 l wal pc *4, 5 t pcl t pcl 1 *3 1 *5 t pcl *4, 5 t pcl pca *4 t pcal t pcal 11t pcal *4 t pcal ref t refc t refc t refc t refc t refc t refc selfx l lock l lock l lock l lock l lock l lock *1
17 MB81N643289-50/-60 preliminary (ae1e) n state diagram (continued) minimum clock latency or delay time for multiple bank operation notes: *1. assume pca command does not affect any operation on the other bank(s). *2. assume no i/o conflict. *3. t ras must be satisfied. *4. assume all outputs are in high-z state. *5. assume applicable bank is in idle state. *6. assume all other banks are in idle state. *7. assume the other bank(s) is in active state and l rcd or l rcdw is satisfied. *8. assume the other bank(s) is in active state and t ras is satisfied. *9. second command have to follow the minimum clock latency or delay time of single bank operation in other bank (second command is asserted.) *10. assume other banks are not in rd/rda/wr/wra state. illegal command. second command (other bank) mrs actv rd rda wr wra pc pca ref self first command mrs l rsc l rsc l rsc l rsc l rsc l rsc actv *5 l rrd *10 1 *3, 10 1 *2, 10 1 *2, 10 11t ras rd *5 1 l cbd *8 l cbd *2 l rwl *2, 8 l rwl 1 *3 l rpl rda *6 l rda *5 1 *4 l cbd *3 l cbd *2 l rwl *2 l rwl 1l rda *6 l rda *4, 6 l rda wr *5 1l wrd *3 l wrd l cbd *3 l cbd 1 *3 l wpl wra *6 l wal *5 1l wrd *3 l wrd l cbd l cbd 1l wal *6 l wal *6 l wal pc *6 t pcl *5 1 *10 1 *3, 10 1 *2, 10 1 *2, 10 11 *3 1 *6 t pcl *4, 6 t pcl pca t pcal t pcal 11t pcal *4 t pcal ref t refc t refc t refc t refc t refc t refc selfx l lock l lock l lock l lock l lock l lock *8 *1, 8 *9 *7 *7 *7 *7
18 MB81N643289-50/-60 preliminary (ae1e) n state diagram (continued) power down self refresh idle (standby) auto refresh mode register fig. 2 C state diagram (simplified for single bank operation) write page close read page close write page open read page open pden self selfx actv mrs definition of allows command input automatic return wr rd active pdex wra rda pc or pca ref wra rda
19 MB81N643289-50/-60 preliminary (ae1e) n functional description ddr, double data rate function the regular sdram read and write cycle have only used the rising edge of external clock input. when clock signal goes to high from low at the read mode, the read out data will be available at every rising clock edge after the specified latency up to burst length. the MB81N643289 ddr fcram features a twice of data transfer rate within a same clock period by transferring data at every rising and falling clock edge. refer to figure 3 in page 24. fcram tm the MB81N643289 utilizes fcram core technology. the fcram is an acronym of fast cycle random access memory and provides very fast random cycle time, low latency and low power consumption than regular drams. clock (clk, clk ) the MB81N643289 adopts differential clock scheme. clk is a master clock and its rising edge is used to latch all command and address inputs. clk is a complementary clock input. the MB81N643289 implements delay locked loop (dll) circuit. this internal dll tracks the signal cross point between clk and clk and generate some clock cycle delay for the output buffer control at read mode. the internal dll circuit requires some lock-on time for the stable delay time generation. in order to stabilize the delay, a constant stable clock input for l lock period is required during the power-up initialization and a constant stable clock input for l lock period is also required after self-refresh exit as specified l lock prior to the any command. power down (pd ) pd is a synchronous input signal and enables power down mode. when all banks are in idle state, pd controls power down (pd) and self-refresh mode. the pd and self-refresh is entered when pd is brought to low and exited when it returns to high. during the power down and self-refresh mode, both clk and clk are disabled after specified time. pd does not have a clock suspend function unlike cke pin of regular sdrams, and it is illegal to bring pd into low if any read or write operation is being performed. for the detail, refer to timing diagrams. it is recommended to maintain pd to be low until v dd gets in the specified operating range in order to assure the power-up initialization. chip select (cs ) cs enables all commands inputs, ras , cas , and we , and address input. when cs is high, all command signals are negated but internal operation such as burst cycle will not be suspended. command inputs (ras , cas and we ) as well as regular sdrams, each combination of ras , cas and we input in conjunction with cs input at a rising edge of the clk determines fcram operation. refer to function truth table in page 5.
20 MB81N643289-50/-60 preliminary (ae1e) n functional description (continued) bank address (ba 0 to ba 2 ) the MB81N643289 has eight internal banks and each bank is organized as 256k words by 32-bit. bank selection by ba occurs at bank active command (actv) followed by read (rd or rda), write (wr or wra), and page close(pc) command. address inputs (a 0 to a 10 ) address input selects an arbitrary location of a total of 2,097,152 words of each memory cell matrix within each bank. a total of twenty address input signals are required to decode such a matrix. the MB81N643289 adopts an address multiplexer in order to reduce the pin count of the address line. at a bank active command (actv), eleven row addresses are initially latched as well as three bank addresses and the remainder of seven column addresses are then latched by a column address strobe command of either a read command (rd or rda) or write command (wr or wra). data strobe (dqs 0 to dqs 3 ) dqs 0 to dqs 3 are bi-directional signal and represent byte 0 to byte 3, respectively. during read operation, dqs 0 to dqs 3 provides the read data strobe signal that is intended to use input data strobe signal at the receiver circuit of the controller(s). it turns low before first data is coming out and toggle high to low or low to high till end of burst read. refer to figure 3 for the timing example. the cas latency is specified to the first low to high transition of these dqs 0 to dqs 3 output. during the write operation, dqs 0 to dqs 3 are used to latch write data and data mask signals. as well as the behavior of read data strobe, the first rising edge of dqs 0 to dqs 3 input latches first input data and following falling edge of dqs 0 to dqs 3 signal latches second input data. this sequence shall be continued till end of burst count. therefore, dqs 0 to dqs 3 must be provided from controller that drives write data. note that dqs 0 to dqs 3 input signal should not be tristated from high at the end of write mode. data inputs and outputs (dq 0 to dq 31 ) input data is latched by dqs 0 to dqs 3 input signal and written into memory. after the (cl-1) clock cycle from the write command, data input is started from the rising edge of dqs. output data is obtained together with dqs 0 to dqs 3 output signals at programmed read cas latency. the polarity of the output data is identical to that of the input. data is valid after dqs 0 to dqs 3 output signal transitions (t qsq ) as specified in data valid time (t qsqv ). write data mask (dm 0 to dm 3 ) dm 0 to dm 3 are active high enable inputs and represent byte 0 to byte 3 respectively. dm 0 to dm 3 have a data input mask function, and are also sampled by dqs 0 to dqs 3 input signal together with input data. during write cycle, dm 0 to dm 3 provide byte mask function. when dmx = high is latched by a dqs 0 to dqs 3 signal edge, data input at the same edge of dqs 0 to dqs 3 is masked. during read cycle, the dm 0 to dm 3 inactive and does not have any effect on read operation. refer to dm truth table in page 6.
21 MB81N643289-50/-60 preliminary (ae1e) n functional description (continued) burst mode operation and burst type the burst mode provides faster memory access and MB81N643289 read and write operations are burst oriented. the burst mode is implemented by keeping the same row address and by automatic strobing column address in every single clock edge till programmed burst length(bl). access time of burst mode is specified as t ac . the internal column address counter operation is determined by a mode register which defines burst type(bt) and burst count length(bl) of 2, 4 or 8 bits of boundary. the burst type is sequential only. the sequential mode is an incremental decoding scheme within a boundary address to be determined by count length, it assigns +1 to the previous (or initial) address until reaching the end of boundary address and then wraps round to the least significant address(= 0). if the first access of column address is even (0), the next address will be odd (1), or vice-versa. burst length starting column address a 2 a 1 a 0 sequential mode 2 x x 0 0 C 1 x x 1 1 C 0 4 x 0 0 0 C 1 C 2 C 3 x 0 1 1 C 2 C 3 C 0 x 1 0 2 C 3 C 0 C 1 x 1 1 3 C 0 C 1 C 2 8 0 0 0 0 C 1 C 2 C 3 C 4 C 5 C 6 C 7 0 0 1 1 C 2 C 3 C 4 C 5 C 6 C 7 C 0 0 1 0 2 C 3 C 4 C 5 C 6 C 7 C 0 C 1 0 1 1 3 C 4 C 5 C 6 C 7 C 0 C 1 C 2 1 0 0 4 C 5 C 6 C 7 C 0 C 1 C 2 C 3 1 0 1 5 C 6 C 7 C 0 C 1 C 2 C 3 C 4 1 1 0 6 C 7 C 0 C 1 C 2 C 3 C 4 C 5 1 1 1 7 C 0 C 1 C 2 C 3 C 4 C 5 C 6
22 MB81N643289-50/-60 preliminary (ae1e) n functional description (continued) page close and page close option (pc, pca) the ddr fcram memory core is the same as conventional drams, requiring page close and refresh operations. page close rewrites the bit line and to reset the internal row address line and is executed by the page close operation (pc or pca). with the page close operation, ddr sdram will automatically be in standby state after specified precharge time (t pcl ). the page closed bank is selected by combination of ac and bank address (ba) when page close command is issued. if ac = high, all banks are page closed regardless of ba (pca command). if ac = low, a bank to be selected by ba is page closed (pc command). the auto-pageclose enters page close mode at the end of burst mode of read or write without page close command issue. this auto-pageclose is entered by ac = high when a read (rd) or write (wr) command is issued. refer to function truth table. auto-refresh (ref) auto-refresh uses the internal refresh address counter. the MB81N643289 auto-refresh command (ref) automat- ically generates bank active and page close command internally. all banks of sdram should be page closed prior to the auto-refresh command. the auto-refresh command should also be issued within every 8 m s period. self-refresh entry (self) self-refresh function provides automatic refresh by an internal timer as well as auto-refresh and will continue the refresh operation until cancelled by selfx. the self-refresh mode is entered by applying an auto-refresh command in conjunction with pd = low (self). once MB81N643289 enters the self-refresh mode, all inputs except for pd can be either logic high or low level state and outputs will be in a high-z state. during self-refresh mode, pd = low should be maintained. self command should only be issued after last read data has been appeared on dq. note: when the burst refresh method is used, a total of 4096 auto-refresh commands within 4 ms must be asserted prior to the self-refresh mode entry. self-refresh exit (selfx) to exit self-refresh mode, pd must bring to high for at least 2 clock cycles together with nop condition. refer to timing diagram for the detail procedure. it is recommended to issue at least one auto-refresh command just after the t rc period to avoid the violation of refresh period. warning:a stable clock for l lock period with a constant duty cycle must be supplied prior to applying any command to insure the dll is locked against the latest device conditions. note: when the burst refresh method is used, a total of 4096 auto-refresh commands within 4 ms must be asserted both before the self-refresh entry and after the self-refresh exit.
23 MB81N643289-50/-60 preliminary (ae1e) n functional description (continued) mode register set (mrs) the mode register of sdram provides a variety of different operations. the register consists of four operation fields; burst length, burst type, cas latency, and test mode entry (this test mode entry must not be used.) refer to mode register table in page 25. the mode register can be programmed by the mode register set command (mrs). each field is set by the address line. once a mode register is programmed, the contents of the register will be held until re-programmed by another mrs command (or part loses power). mrs command should only be issued on condition that all banks are in idle state and all dqs are in high-z. the condition of the mode register is undefined after the power-up stage. it is required to set each field at power-up initialization. refer to power-up initialization below. note: the extended mode register set command (emrs) and its dll enable function of emrs field is only used at power-on sequence. power-up initialization the MB81N643289 internal condition at and after power-up will be undefined. since MB81N643289 adopts the method for two power supplies, which has two different power supply pins for internal core and i/o, it is required to follow the following power on sequence to execute read or write operation. 1. apply v dd voltage to all v dd pins before or at the same time as v ddq pins and attempt to maintain all input signals to be low state (or at least pd to be low state). 2. apply v dd voltage to all v ddq pins before or at the same time as v ref . 3. apply v ref . 4. start clock after all power supplies reached in a specified operating range and maintain stable condition for a minimum of 200 m s. 5. after the minimum of 200 m s stable power and clock, apply nop condition and take pd to be high state. 6. issue page close all banks (pca) command or page close single bank (pc) command to every banks. 7. issue emrs to enable dll, de = low. 8. issue mode register set command (mrs) to reset dll, dr = high. an additional clock input for l lock * 1 period is required to lock the dll. 9. apply minimum of two auto-refresh command (ref).* 2 10. program the mode register by mode register set command (mrs) with dr = low.* 2 notes: *1. the l lock depends on operating clock period. the l lock is counted from dll reset at step-8 to any command input at step-10. *2. the mode register set command (mrs) can be issued before two auto-refresh cycle (ref). power-down the MB81N643289 uses multiple power supply voltage. it is required to follow the reversed sequence of above power on sequence. 1. take all input signals to be v ss or high-z. 2. deapply v ddq . 3. deapply v dd after or at the same time as v ddq .
24 MB81N643289-50/-60 preliminary (ae1e) n functional description (continued) fig. 3 C sdram read timing example (@ cl=2 & bl=2) clk (external) data command rd < ddr sdram > hi-z rd q1 hi-z q2 q1 q2 clk data command clk t0 t1 t2 t3 t4 t0 t0.5 t1 t1.5 t2 t2.5 t3 t3.5 t4 stored by clk input stored by clk input output in every rising clk edge output in every cross point of clock input dqs signal tran- sition occurs at the same time as data bus. dqs hi-z low high
25 MB81N643289-50/-60 preliminary (ae1e) n mode register table mode register set address ba 2 ba 1 ba 0 a 10 a 9 a 8 a 7 a 6 - a 4 a 3 a 2 - a 0 register 0 *1 0 *1 0 *1 0 1 *2 dr te cl bt bl a 6 a 5 a 4 cas latency (cl) 0 0 x reserved 010 2 * 5 011 3 * 5 100 reserved 101 reserved 110 reserved 111 reserved a 2 a 1 a 0 burst length (bl) 000 reserved 001 2 010 4 011 8 1 x x reserved a 7 test mode entry (te) 0 normal operation 1 test mode (used for supplier test mode) a 3 burst type (bt) 0 sequential (wrap round, binary up) 1 reserved a 8 dll reset (dr) 0 normal operation 1 reset dll extended mode register set (note *4) notes: *1. a combination of ba 2 = ba 1 = ba 0 = 0 (low) selects standard mode register. *2. this field must be set as 1. *3. a combination of ba 1-2 = 0 and ba 0 = 1 (high) selects extended mode register. *4. the reserved field must be set as 0. *5. write latency (wl) = cl-1 address ba 2 ba 1 ba 0 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 extended mode register 0 *3 0 *3 1 *3 reserved * 4 de a 0 dll enable (de) 0dll enable 1dll disable
26 MB81N643289-50/-60 preliminary (ae1e) n absolute maximum ratings (see warning) warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n recommended operating conditions (referenced to v ss ) parameter symbol value unit voltage of v dd supply relative to v ss v dd , v ddq C0.5 to +3.6 v voltage at any pin relative to v ss v in , v out C0.5 to +3.6 v short circuit output current i out 50 ma power dissipation p d 2.0 w storage temperature t stg C55 to +125 c parameter notes symbol min. typ. max. unit supply voltage v dd 2.3 2.5 2.7 v v ddq v dd v dd v dd v v ss , v ssq 00 0v input reference voltage *3 v ref v ddq /2 *98% (1.15v min) v ddq /2 v ddq /2 *102% (1.35v max) v single ended dc input high level v ih(dc) v ref + 0.25 v ddq + 0.1 v single ended dc input low level v il(dc) C0.1 v ref C 0.25 v single ended ac input high level *1 v ih(ac) v ref + 0.35 v ddq + 0.1 v single ended ac input low level *2 v il(ac) C0.1 v ref C 0.35 v differential dc level input voltage v in(dc) C0.1 v ddq + 0.1 v differential dc level differential input voltage v swing(dc) 0.50 v ddq + 0.2 v differential ac level differential input voltage v swing(ac) 0.70 v ddq + 0.2 v differential ac level input cross point voltage v x(ac) v ddq /2 C 0.2 v ddq /2 v ddq /2 + 0.2 v differential input signal offset voltage *4 v iso(ac) v ddq /2 C 0.2 v ddq /2 v ddq /2 + 0.2 v ambient temperature t a 070 c
27 MB81N643289-50/-60 preliminary (ae1e) n recommended operating conditions (continued) notes: *3. v ref is expected to track variations in the dc level of v ddq of the transmitting device. peak-to-peak noise level on v ref may not exceed +/- 2% of the supplied dc value. *4. v iso means {v in(clk) + v in(clk ) } / 2. refer to differential input signal definition. warning: recommended operating conditions are normal operating ranges for the semiconductor device. all the devices electrical characteristics are warranted when operated within these ranges. always use semiconductor devices within the recommended operating conditions. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representative beforehand. differential input signal definition n capacitance (t a = 25 c, f = 1 mhz) parameter symbol min. typ. max. unit input capacitance, address & control c in1 2.5 3.5 pf input capacitance, clk & clk c in2 2.5 3.5 pf input capacitance, dm 0 to dm 3 c in3 4.0 5.5 pf i/o capacitance c i/o 4.0 5.5 pf *2. undershoot limit: v il (min) v dd + 1v vih vil pulse width 4 ns *1. overshoot limit: v ih (max) 50% of pulse amplitude vih vil -1.0v pulse width measured at 50% of pulse amplitude. = v dd + 1v for pulse width <= 4 ns acceptable, = v ss - 1.0v for pulse width <= 4 ns acceptable, pulse width measured at 50% of pulse amplitude. 50% of pulse amplitude pulse width 4 ns vih min vil max fig. 4 C differential input signal offset voltage (for clock input) v iso (max.) v iso (min.) clk v swing(ac) v x clk v ss |v swing | 0v differential v iso v ss
28 MB81N643289-50/-60 preliminary (ae1e) n dc characteristics (at recommended operating conditions unless otherwise noted.) note *1,*2,*3 (continued) parameter symbol condition value unit min. max. output minimum source dc current *4 i oh(dc) v ddq = 2.3v for min, 2.7v for max v oh = v ddq -0.2v -4.0 -6.8 ma output minimum sink dc current *4 i ol(dc) v ddq = 2.3v for min, 2.7v for max v ol = +0.2v 4.0 6.8 ma input leakage current (any input) i li 0 v < v in < v dd ; all other pins not under test = 0 v -10 10 m a output leakage current i lo 0 v < v in < v dd ; data out disabled -10 10 m a v ref current i ref -10 10 m a operating current (average power supply current) MB81N643289-50 i dd1s burst length = 2 t ck = min, t rc = min for bl = 2 one bank active, address change up to 3 times during t rc (min) 0 v < v in < v il (max), v ih (min) < v in < v dd 450 ma MB81N643289-60 385 standby current MB81N643289-50 i dd2n pd = v ih , t ck = min all banks idle, nop commands only, input signals (except to cmd) are changed one time during 20 ns 0 v < v in < v il (max), v ih (min) < v in < v dd 85 ma MB81N643289-60 75 power down current i dd2p pd = v il , t ck = min all banks idle, 0 v < v in < v dd 35ma active standby current (power supply current) MB81N643289-50 i dd3n pd = v ih , t ck = min all banks active, nop commands only, input signals (except to cmd) are changed one time during 20 ns 0 v < v in < v il (max), v ih (min) < v in < v dd 235 ma MB81N643289-60 200
29 MB81N643289-50/-60 preliminary (ae1e) (continued) notes: *1. all voltages referenced to v ss . *2. dc characteristics are measured after following the power-up initialization procedure. *3. i dd depends on the output termination or load conditions, clock cycle rate, and number of address and command change within certain period. the specified values are obtained with the output open. *4. refer to output characteristics for the detail. parameter symbol condition value unit min. max. bust read current (average power supply current) MB81N643289-50 i dd4r burst length = 4, cas latency = 3, all bank active, gapples data, t ck = min, 0 v < v in < v il (max), v ih (min) < v in < v dd 510 ma MB81N643289-60 430 bust write current (average power supply current) MB81N643289-50 i dd4w burst length = 4, cas latency = 3, all bank active, gapless data, t ck = min, 0 v < v in < v il (max), v ih (min) < v in < v dd 595 ma MB81N643289-60 505 auto-refresh current (average power supply current) MB81N643289-50 i dd5 auto-refresh; t ck = min, t refc = min 0 v < v in < v il (max), v ih (min) < v in < v dd 320 ma MB81N643289-60 270 self-refresh current (average power supply current) i dd6 self-refresh; pd = v il , 0 v < v in < v dd 5ma
30 MB81N643289-50/-60 preliminary (ae1e) n dc characteristics (continued) output characteristics v ol (v) current(ma) min max 000 0.4 11.1 11.3 0.8 21.6 22.1 1.2 31.1 32.3 1.6 39.2 41.6 2.0 44.6 49.9 2.4 46.4 56.3 2.8 n/a 55.8 min max 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 v ol (v) 60 50 40 30 20 10 0 current(ma) fig. 5 C pull-down characteristics v dd - v oh (v) current(ma) min max 000 0.4 -10.5 -11.0 0.8 -20.1 -21.6 1.2 -28.6 -31.8 1.6 -35.2 -41.6 2.0 -38.7 -50.7 2.4 -40.9 -59.0 2.8 n/a -60.4 min max 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 v dd - v oh (v) 0 -10 -20 -30 -40 -50 -60 -70 current(ma) fig. 6 C pull-up characteristics
31 MB81N643289-50/-60 preliminary (ae1e) n ac characteristics (recommended operating conditions unless otherwise noted.) note *1,*2,*3 ac parameters (cas latency dependent) ac parameters (absolute bales) base values for clock count/latency (note *7) parameter symbol MB81N643289-50 MB81N643289-60 unit min. max. min. max. clock period t ck cl = 3 5.0 9.0 6.0 10.5 ns cl = 2 7.5 10.5 9.0 10.5 parameter notes symbol MB81N643289-50 MB81N643289-60 unit min. max. min. max. input setup time (except for dqs, dm and dqs) *4 t is 1.0 1.2 ns input hold time (except for dqs, dm and dqs) *4 t ih 1.0 1.2 ns data input setup time *5 t ds 0.6 0.7 ns data input hold time *5 t dh 0.6 0.7 ns dqs first input setup time (input preamble setup time) *4 t dspres 00ns input transition time *6 t t 0.1 0.8 0.1 0.9 ns power down exit and self-refresh exit time *4 t pde 3.0 3.6 ns parameter notes symbol MB81N643289-50 MB81N643289-60 unit min. max. min. max. random cycle time t rc 30 36 ns active to page close time t ras 20 55000 24 55000 ns page close single bank to active t pcl 10 12 ns page close all bank to active t pcal 20 24 ns auto-refresh cycle time *8 t refc 60 72 ns auto-refresh interval *8 t refi 8.0 8.0 m s time between refresh *8 t ref 3232ms pause time after power-on *9 t pause 200 200 m s
32 MB81N643289-50/-60 preliminary (ae1e) n ac characteristics (continued) ac parameters (frequency dependant) note *10 parameter notes symbol min. max. unit clock high time *4 t ch 0.45 * t ck ns clock low time *4 t cl 0.45 * t ck ns dqs low to high input transition setup time from clk *4, *11 t dqss (cl C 1 C 0.25) * t ck (cl C 1 + 0.25) * t ck ns dqs first low input hold time (input preamble hold time) *4 t dspreh 0.25 * t ck ns dqs first low input pulse width (input preamble pulse width) t dspre 0.4 * t ck 0.6 * t ck ns dqs last low input hold time (input postamble hold time) t dspst 0.4 * t ck 0.6 * t ck ns dq, dqs, dm input pulse width t dipw 0.35 * t ck ns dqs input falling edge to clock setup time t dss 0.2 * t ck (1.5 ns min) ns dqs input falling edge to clock hold time t dsh 0.2 * t ck (1.5 ns min) ns qs access time from clock *4 t ckqs C 0.1 * t ck C 0.2 0.1 * t ck + 0.2 ns data access time from clk *4 t ac C 0.1 * t ck C 0.2 0.1 * t ck + 0.2 ns data output valid time t oh C 0.1 * t ck C 0.2 0.1 * t ck + 0.2 ns dqs output in low-z (output preamble setup time) *4, *12 t qslz C 0.1 * t ck C 0.2 ns dqs first low output hold time (output preamble hold time) *4 t qspre 0.9 * t ck C 0.2 1.1 * t ck + 0.2 ns dqs last low output hold time (output postamble hold time) *4, *13 t qspst 0.4 * t ck C 0.2 0.6 * t ck + 0.2 ns dqs last low output in high-z from clk to clk *4, *13 t qshz 0.1 * t ck + 0.2 ns qs pulse width t qsp 0.4 * t ck C 0.2 ns data output valid time from dqs t qsqv 0.4 * t ck C 0.4 ns data output skew from dqs *5 t qsq C 0.1 * t ck 0.1 * t ck ns dq output in low-z *4, *12 t lz C 0.1 * t ck C 0.2 ns dq output in high-z *4, *13 t hz C 0.1 * t ck C 0.2 0.1 * t ck + 0.2 ns
33 MB81N643289-50/-60 preliminary (ae1e) n ac characteristics (continued) example of frequency dependant ac parameters (@ minimum t ck ) parameter symbol t ck = 5ns t ck = 6ns t ck = 7.5ns t ck = 9ns t ck = 10.5ns unit min. max. min. max. min. max. min. max. min. max. clock high time t ch 2.3 2.7 3.4 4.1 4.8 ns clock low time t cl 2.3 2.7 3.4 4.1 4.8 ns dqs low to high input transition setup time from clk cl=2 t dqss 3.8 6.3 4.5 7.5 5.7 9.4 6.8 11.3 7.9 13.2 ns cl=3 8.8 11.3 10.5 13.5 13.2 16.9 15.8 20.3 18.4 23.7 dqs first low input hold time (input preamble hold time) t dspreh 1.3 1.5 1.9 2.3 2.7 ns dqs first low input pulse width (input preamble pulse width) t dspre 2.0 3.0 2.4 3.6 3.0 4.5 3.6 5.4 4.2 6.3 ns dqs last low input hold time (input postamble hold time) t dspst 2.0 3.0 2.4 3.6 3.0 4.5 3.6 5.4 4.2 6.3 ns dq, dqs, dm input pulse width t dipw 1.8 2.1 2.7 3.2 3.7 ns dqs input falling edge to clock setup time t dss 1.5 1.5 1.5 1.8 2.1 ns dqs input falling edge to clock hold time t dsh 1.5 1.5 1.5 1.8 2.1 ns qs access time from clock t ckqs C0.7 0.7 C0.8 0.8 C1.0 1.0 C1.1 1.1 C1.3 1.3 ns data access time from clk t ac C0.7 0.7 C0.8 0.8 C1.0 1.0 C1.1 1.1 C1.3 1.3 ns data output valid time t oh C0.7 0.7 C0.8 0.8 C1.0 1.0 C1.1 1.1 C1.3 1.3 ns dqs output in low-z (output preamble setup time) t qslz C0.7 C0.8 C1.0 C1.1 C1.3 ns dqs first low output hold time (output preamble hold time) t qspre 4.3 5.7 5.2 6.8 6.6 8.5 7.9 10.1 9.3 11.8 ns dqs last low output hold time (output postamble hold time) t qspst 1.8 3.2 2.2 3.8 2.8 4.7 3.4 5.6 4.0 6.5 ns dqs last low output in high-z from clk to clk t qshz 0.7 0.8 1.0 1.1 1.3 ns qs pulse width t qsp 1.8 2.2 2.8 3.4 4.0 ns data output valid time from dqs t qsqv 1.6 2.0 2.6 3.2 3.8 ns data output skew from dqs t qsq C0.5 0.5 C0.6 0.6 C0.8 0.8 C0.9 0.9 C1.1 1.1 ns dq output in low-z t lz C0.7 C0.8 C1.0 C1.1 C1.3 ns dq output in high-z t hz C0.7 0.7 C0.8 0.8 C1.0 1.0 C1.1 1.1 C1.3 1.3 ns
34 MB81N643289-50/-60 preliminary (ae1e) n ac characteristics (continued) minimum latency - fixed values (the latency values on these parameters are fixed regardless of clock period.) parameter symbol bl = 2 bl = 4 bl = 8 unit ras (act) to cas (read) delay (minimum) (applicable to same bank) cl = 3 l rcd 333t ck cl = 2 2 2 2 t ck ras (act) to cas (write) delay (minimum) (applicable to same bank) cl = 3 l rcdw 111t ck cl = 2 1 1 1 t ck write command to read command delay time (applicable to other bank in page open) cl = 3 l wrd 235t ck cl = 2 2 3 5 t ck read with auto-close to next command input delay (applicable to same bank) cl = 3 l rda 346t ck cl = 2 3 4 6 t ck write with auto-close command to next command input delay (applicable to same bank) cl = 3 l wal 7810t ck cl = 2 6 7 9 t ck read to page close command delay (applicable to same bank) cl = 3 l rpl 124t ck cl = 2 1 2 4 t ck write to page close command delay (applicable to same bank) cl = 3 l wpl 568t ck cl = 2 4 5 7 t ck cas to cas delay (applicable to same bank) cl = 3 l ccd 124t ck cl = 2 1 2 4 t ck cas to cas bank delay (applicable to other bank) cl = 3 l cbd 124t ck cl = 2 1 2 4 t ck read command to write command lead time (applicable to any bank in page open) cl = 3 l rwl 346t ck cl = 2 3 4 6 t ck write command to read command lead time (applicable to same bank) cl = 3 l wrl 568t ck cl = 2 4 5 7 t ck mode register set cycle time cl = 3 l rsc 222t ck cl = 2 2 2 2 t ck power down exit to next command input delay (minimum) cl = 3 l pdex 222t ck cl = 2 2 2 2 t ck active command to next active (applicable to other bank) cl = 3 l rrd 111t ck cl = 2 1 1 1 t ck pd low to command/address input inactive cl = 3 l pd 111t ck cl = 2 1 1 1 t ck clock lock-on time *14 t ck < 7.5 ns l lock 400 400 400 t ck 7.5 to t ck(max) 630 630 630 t ck
35 MB81N643289-50/-60 preliminary (ae1e) n ac characteristics (continued) notes: *1. ac characteristics are measured after following the power-up initialization procedure and stable clock input with constant clock period and with 50% duty cycle. *2. access times assume input slew rate of 1ns/volt between v ref +0.35v to v ref -0.35v, where v ref is v ddq /2, with 1 resistor and 1 capacitor load conditions. refer to ac test load circuit in page 36. *3. v ref = 1.25v is a typical reference level for measuring timing of input signals. transition times are measured between v ih (min) and v il (max) unless otherwise noted. refer to ac test conditions in page 36. *4. this parameter is measured from the cross point of clk and clk input. *5. this parameter is measured from signal transition point of dqs input crossing v ref level. *6. t t is defined as the transition time between v ih (ac) (min) and v il (ac) (max). *7. all base values are measured from the cross point of the rising edge of clk and falling edge of clk at the command input to the cross point of same clock input condition for the next command input. all clock counts (= latency) are calculated by a simple formula: clock count equals base value divided by clock period (round off to a whole number). *8. total of 4096 ref command must be issued within t ref (max). t refc is a reference value for distributed refresh and specifies the time between one ref command to next ref command except for a condition where pd = l during self-refresh mode. *9. specified when the clock input is started on the condition of the stable supply voltage. *10. frequency dependent ac parameters are scalable by actual clock period (t ck ) and affected by an abrupt change of duty cycle, jitters on clock input, t a and level of v dd and v ddq . the internal dll circuit can adjust delay time to change and following level change of v dd and v ddq , (change rate of t a < 0.1 c / 20 ns, change rate of v dd and v ddq < 1 mv / 10 ns. if change rate is bigger than these value, frequency dependent ac parameters affected by jitters causing by these change.) *11. more than 2 signal edge of dqs 0-3 should not be input within 1 clock (t ck ) cycle. *12. low-z (low impecdnce state) is specified and measured at v dd / 2 +/- 200 mv from standby state. *13. t hz are specified where output buffer is no longer driven. *14. clock period must satisfy specified t ck and it must be stable. applicable also if device operating conditions such as supply voltages, case temperature, and/or clock frequency (t ck difference must be 0.2 ns and under) is changed during any operation. clock > (round off a whole number) base value clock period
36 MB81N643289-50/-60 preliminary (ae1e) n ac characteristics (continued) ac test conditions v x means the actual cross point between clk and clk input. parameters symbol value unit single-end input input high level v ih v ref +0.35 v input low level v il v ref -0.35 v input reference level v ref v ddq /2 v input slew rate slew 1.0 v/ns differential input (clk and clk ) input reference level vr v x(ac) v input level v swing 0.7 v input slew rate slew 1.0 v/ns output fig. 7 C example of ac test load circuit (2.5 v cmos source termination) r = 50 w cl = 20 pf v ddq /2 note: by adding appropriate correlation factors to the test conditions, tac and toh measured when the output is coupled to the output load circuit are within specifications.
37 MB81N643289-50/-60 preliminary (ae1e) n ac characteristics (continued) note: reference level for ac timings of clock are the cross point of clk and clk as specified in v x . fig. 8 C ac timing of clk & clk t cl t ck t oh clk v swing(ac) v x clk t is t ih input (controls & addresses) fig. 9 C ac timing of command input & address v ref input valid v ih (ac) v il (ac) t ck v x clk note: the cross point of clk and clk (v x ) is used for command and address input. the reference level of single ended input is v ref . clk input (data&dm) fig. 10 C ac timing of write mode (data strobe, write data and data mask input) t ds t dh t ds t dh v ref v il dqs input (@bl=4) input valid input valid t ck t ck clk clk t is t ih input (controls & addresses) v ref write command v ih (ac) v il (ac) t dqss v ref t ds t dh t ds t dh input valid input valid t dspst t dspres t dspreh t dqss t dspre t dss t dsh t dipw t dipw t dipw t dipw
38 MB81N643289-50/-60 preliminary (ae1e) n ac characteristics (continued) note: dqs access time (t qsck ) is measured from the cross point of clock (v x ) and v ref . the end of t qspst and t qshz specification is defined at where output buffer is no longer driven. fig. 11 C ac timing of read mode (clock to dqs output delay time) v il dqs output (@bl=4) t ckqs (min) t ck v x clk clk t qspre t ckqs (max) t qspst t ckqs (min) t ckqs (max) t ckqs (min) t ckqs (max) t ckqs (min) t ckqs (max) t ck hi-z t qslz (min) t qshz t qsp t qsp t qsp dq data output (@bl=4) note: access time (t ac ) is measured from the cross point of clock (v x ) and v ref . the end of t hz specification is defined at where output buffer is no longer driven. fig. 12 C ac timing of read mode (clock to data output delay time) v ih v il t ck v x clk clk t ac (min) t lz (min) t ac (max) t ck t ac (min) t ac (max) t ac (min) t ac (max) t ac (min) t ac (max) t oh (max) t hz (max) t oh (min) hi-z dq data output (@bl=4) note: dqs output edge to data output edge skew time (t qsq ) is measured from v ddq /2 to v ddq /2. fig. 13 C ac timing of read mode (dqs output to data output delay time) v ih v il v ref dqs output (@bl=4) t qsq (min) t qsqv t qsqv t qsq (max) t qsqv t qsqv t qsq (min) t qsq (max) t qsq (min) t qsq (max) t qsq (min) t qsq (max) hi-z
39 MB81N643289-50/-60 preliminary (ae1e) n ac characteristics (continued) fig. 14 C ac timing, pulse width t rc , t ras , t pcal , t ref , t refi , t refc , t pau s e clk input (controls & addresses) note: all parameters listed above are measured from the cross point at rising edge of the clk and falling edge of clk of one command input to next command input. command command clk v x v x pd clk pden command l pdex (min) nop actv fig. 15 C ac timing of power down mode pdex nop dont care t pde t rc (min), t ref (max) clk note: minimum 2 clock cycles is required for complete power down on clock buffer. v ref nop l pd pd clk t is self command l lock (min) nop actv fig. 16 C ac timing of self-refresh mode nop nop dont care t pde clk note: 1. minimum 2 clock cycles is required for complete power down on clock buffer. 2pd must maintain high level and clock must be provided during the l lock period. l lock must be satisfied before any command input. v ref note *1 t refc (min) *2 l pd nop
40 MB81N643289-50/-60 preliminary (ae1e) n timing diagrams timing diagram C 1 : page mode read (timing assumes same bank access) clk dq (output) @cl = 3 dqs (output) @cl = 3 actv command clk nop rd pc nop nop q1 q2 q1 q2 l rcd l rpl rd actv q1 q2 t pcl l ccd rd rda nop hi-z hi-z cl cl cl t ras dq (output) @cl = 2 dqs (output) @cl = 2 q1 q2 q1 q2 q1 q2 hi-z hi-z cl cl cl notes: 1. l rcd :latency of actv to read command input delay. 2. l ccd :latency of cas to cas delay (page cycle time). 3. l rpl :latency of read command to page close lead time. 4. t pcl :page close to next command lead time.
41 MB81N643289-50/-60 preliminary (ae1e) timing diagram C 2 : random read with auto-close (timing assumes cl=3, same bank access) clk dq (output) @bl = 4 dqs (output) @bl = 4 note: l rda : latency of read with auto close command. actv command clk nop rda nop actv nop rda nop actv q1 q2 q3 q4 q1 q2 q3 q4 l rcd l rda hi-z hi-z cl cl dq (output) @bl = 2 dqs (output) @bl = 2 actv command nop rda actv nop rda nop actv q1 q2 q1 q2 l rcd l rda nop nop hi-z hi-z cl cl dq (output) @bl = 8 dqs (output) @bl = 8 actv command nop rda nop nop rda q1 q2 l rcd l rda nop hi-z hi-z cl cl actv q1 q2 q3 q4 q5 q6 q7 q8 q3 q4 nop
42 MB81N643289-50/-60 preliminary (ae1e) timing diagram C 3 : random write (timing assumes cl=3, bl=4, same bank access) clk dq (output) dqs (output) actv command clk wr nop nop l rcdw l wpl actv pc nop t pcl notes: 1l rcdw : letency of actv to write command input delay is minimum 1 clock. 2l wpl : latency of write command to auto close command lead time. hi-z hi-z t dqss d1 d2 d3 d4 wl (= cl-1) timing diagram C 4 : random write with auto-close (timing assumes cl=3, bl=4, same bank access) clk dq (output) dqs (output) actv command clk wra nop nop d1 d2 d3 d4 l rcdw l wal actv note: l wal : latency write with auto close command to next active command lead time. hi-z hi-z wl (= cl-1) t dqss
43 MB81N643289-50/-60 preliminary (ae1e) timing diagram C 5 : page mode write (timing assumes cl=3, bl=4, same bank access) clk dq (output) dqs (output) actv command clk wr nop nop l rcdw l wal actv l ccd wra hi-z hi-z wl wl nop d1 d2 d3 d4 d1 d2 d3 d4 timing diagram C 6 : page mode write (timing assumes cl=3, bl=2, same bank access) clk dq (output) dqs (output) actv command clk wr nop l rcdw l wpl actv l ccd wr t pcl nop pc nop hi-z hi-z wl wl d1 d2 d1 d2
44 MB81N643289-50/-60 preliminary (ae1e) l rrd timing diagram C 7 : random read (timing assumes cl=3, bl=4, multiple bank access) clk dq (output) dqs (output) actva command clk nop actvb nop q1 q2 q3 q4 l rcd l rda rdaa q1 q2 q3 q4 rdab nop actva nop actvb rdaa nop l cbd q1 q2 q3 q4 hi-z hi-z cl (bank a) cl (bank b) cl (bank a) notes: 1l cbd : latency of cas to cas bank delay 2l rrd : latency of active command to next active command. l rcd timing diagram C 8 : random read (timing assume cl=3, bl=4, multiple bank access) clk dq (output) dqs (output) actva command clk nop actvb nop q1 q2 q3 q4 l rcd l rda l rrd rda q1 q2 q3 q4 rdb nop rda nop rdb pca nop l cbd q1 q2 q3 q4 nop acvta pcb t pcl q1 q2 q3 q4 hi-z hi-z cl (bank a) cl (bank b) cl (bank a) cl (bank b)
45 MB81N643289-50/-60 preliminary (ae1e) l rrd timing diagram C 9 : random write (timing assumes cl=3, bl=4, multiple bank access) clk dq (output) dqs (output) actva command clk nop actvb nop wraa wrab nop actva nop actvb l cbd hi-z hi-z wl (bank a) wl (bank b) d1 d2 d3 d4 d1 d2 d3 d4 nop l wal l rrd timing diagram C 10 : random write (timing assumes cl=2, bl=4, multiple bank access) clk dq (output) dqs (output) actva command clk nop actvb nop l wpl wra wrb nop actva nop pca nop l cbd pcb t pcl hi-z hi-z wl (bank a) wl (bank b) d1 d2 d3 d4 d1 d2 d3 d4
46 MB81N643289-50/-60 preliminary (ae1e) timing diagram C 11 : random read / write (timing assumes cl=2, bl=2, same bank access) clk dq dqs actv command clk nop rda actv nop wr_ l rcd l rda nop q1 q2 hi-z hi-z cl wl nop d1 d2 timing diagram C 12 : random read / write (timing assumes cl=2, bl=4, same bank access) clk dq dqs actv command clk nop wra actv nop rd_ l wal nop hi-z hi-z wl d1 d2 d3 d4
47 MB81N643289-50/-60 preliminary (ae1e) clk dq dqs actv command clk nop nop q1 q2 q3 q4 l rwl l rcd rd nop wr nop rd l wrl d1 d2 d3 d4 timing diagram C 13 : page mode read / write (timing assumes cl=3, bl=4, same bank access) notes: 1. l rwl : letency of read to write command. 2. l wrl : latency of read to write command in same bank. hi-z hi-z wl cl timing diagram C 14 : page mode read / write (timing assumes cl=3, bl=4, multiple bank access) clk dq dqs actva command clk nop nop q1 q2 q3 q4 l rwl l rcd rda nop wrb pca rda l wrd d1 d2 d3 d4 actvb nop pcb q1 q2 q3 q4 hi-z hi-z notes: 1. l wrd : latency of write to read command in different bank. 2. data strobe input must be applied after or before output of dqs is in high-z. cl (bank a) wl (bank b) cl (bank a)
48 MB81N643289-50/-60 preliminary (ae1e) timing diagram C 15 : page mode read / write (timing assumes cl=3, bl=4, multiple bank access) clk dq dqs actva command clk nop nop l wrd l rcd wra nop rdb pca l rpl actvb nop actv hi-z hi-z wl (bank a) cl (bank b) d1 d2 d3 d4 t pcal q1 q2 q3 q4 nop timing diagram C 16 : auto-refresh (timing assumes cl=2, bl=2) clk dq dqs actv command clk nop rda ref nop any l rda nop q1 q2 hi-z hi-z note: refresh command can be issued all banks has been closed. t refc
49 MB81N643289-50/-60 preliminary (ae1e) timing diagram C 17 : self-refresh (timing assumes cl=2) clk dq pd nop command clk self dont care selfx any t pde l lock nop hi-z nop timing diagram C 18 : power down (timing assumes any cl) clk dq pd nop command clk pden nop pdex nop t pde l pdex any nop hi-z note: l pdex : latency of power down exit to next command input delay. t ref must be satisfied for burst refresh and t aref must be satisfied for distributed refresh.
50 MB81N643289-50/-60 preliminary (ae1e) timing diagram C 19 : mode register set (timing assumes any cl and frequency) clk nop command clk mrs nop nop any l rsc note: l rsc : latency of mode register set to next command lead time.
51 MB81N643289-50/-60 preliminary (ae1e) timing diagram C 20 : power-up initialization clk dq pd command clk pc nop hi-z pca dqs hi-z mrs a 0 to a 9 v dd v ddq v ref t ch t cl t is t ih emrs ref ref act a 10 dr, ra l ra l t pcl t refc t ref l rsc ba 0 l ba h ba 1 ,ba 2 l l v ref l rsc t ck de t pcal l lock ba mrs cl,bl l l l
52 MB81N643289-50/-60 preliminary (ae1e) n scitt test mode about scitt scitt (static component interconnection test technology) is an xnor circuit based test technology that is used for testing interconnection between sdram and sdram controller on the printed circuit boards. scitt provides inexpensive board level test mode in combination with boundary-scan. the basic idea is simple, consider all output of sdram as output of xnor circuit and each output pin has a unique mapping on the input of sdram. the ideal schematic block diagram is as shown below. it is static and provides easy test pattern that result in a high diagnostic resolution for detecting all open/short faults. m c asic sdram controller test control xaddress bus data bus sdram core xnor boundary scan test control : cas, cs , pd xaddress bus : a 0 to a 10 , ba 0 to ba 2 , ras , dm 0 to dm 3 , clk, clk , we data bus : dq 0 to dq 31 , dqs 0 to dqs 3
53 MB81N643289-50/-60 preliminary (ae1e) scitt test sequence the followings are the scitt test sequence. scitt test can be executed after power-on and prior to precharge command in power-up initialization. once precharge command is issued to sdram, it never get back to scitt test mode during regular operation for the purpose of a fail-safe way in get in and out of test mode. 1. apply v dd voltage to all v dd pins before or at the same time as v ddq pins and attempt to maintain all input signals to be low state (or at least pd to be low state). 2. apply v dd voltage to all v ddq pins before or at the same time as v ref . 3. apply v ref . 4. maintain stable power for a minimum of 100 m s. 5. enter scitt test mode. 6. execute scitt test. 7. exit from scitt mode. it is required to follow power on sequence to execute read or write operation. 8. start clock after all power supplies reached in a specified operating range and maintain stable condition for a minimum of 200 m s. 9. after the minimum of 200 m s stable power and clock, apply nop condition and take pd to be high state. 10.issue page close all banks (pca) command or page close single bank (pc) command to every banks. 11.issue emrs to enable dll, de = low. 12.issue mode register set command (mrs) to reset dll, dr = high. an additional clock input for l lock * 1 period is required to lock the dll. 13.apply minimum of two auto-refresh command (ref).* 2 14.program the mode register by mode register set command (mrs) with dr = low.* 2 the 5,6,7 steps define the scitt mode available. it is possible to skip these steps if necessary (refer to power- up initialization). notes: *1. the l lock depends on operating clock period. the l lock is counted from dll reset at step-8 to any command input at step-10. *2. the mode register set command (mrs) can be issued before two auto-refresh cycle. command truth table note *1 notes: *1. l = logic low, h = logic high, v = valid, x = either l or h *2. the scitt mode entry command assumes the first cas falling edge with cs and pd = l after power on. *3. the scitt mode exit command assumes the first cas rising edge after the test mode entry. *4. refer the test code table. *5. cs = h or cke = l is necessary to disable outputs in scitt mode exit. control input output cas cs pd we ras a 0 to a 10 , ba 0 to ba 2 dm 0 to dm 3 clk, clk dq 0 to dq 31 dqs 0 to dqs 3 scitt mode entry h ? l * 2 llxx x x xxx scitt mode exit l ? h * 3 h *5 l *5 xx x xxxx scitt mode output enable * 4 l lhvv v vvvv
54 MB81N643289-50/-60 preliminary (ae1e) test code table dq 0 to dq 31 and dqs 0 to dqs 3 output data is static and is determined by following logic during the scitt mode operation. dq 0 = ras xnor a 0 dq 1 = ras xnor a 1 dq 2 = ras xnor a 2 dq 3 = ras xnor a 3 dq 4 = ras xnor a 4 dq 5 = ras xnor a 5 dq 6 = ras xnor a 6 dq 7 = ras xnor a 7 dq 8 = ras xnor a 8 dq 9 = ras xnor a 9 dq 10 = ras xnor a 10 dq 11 = ras xnor ba 1 dq 12 = ras xnor ba 0 dq 13 = ras xnor ba 2 dq 14 = ras xnor dm 0 dq 15 = ras xnor dm 1 dq 16 = ras xnor dm 2 dq 17 = ras xnor dm 3 dq 18 = ras xnor clk dq 19 = ras xnor clk dq 20 = ras xnor we dq 21 = a 0 xnor a 1 dq 22 = a 0 xnor a 2 dq 23 = a 0 xnor a 3 dq 24 = a 0 xnor a 4 dq 25 = a 0 xnor a 5 dq 26 = a 0 xnor a 6 dq 27 = a 0 xnor a 7 dq 28 = a 0 xnor a 8 dq 29 = a 0 xnor a 9 dq 30 = a 0 xnor a 10 dq 31 = a 0 xnor ba 0 dqs 0 = a 0 xnor ba 1 dqs 1 = a 0 xnor ba 2 dqs 2 = a 0 xnor dm 0 dqs 3 = a 0 xnor dm 1 ? example of test code table input bus output bus 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 h l l h h h h h h h h h h h h h h h h h h h h l l h h h h h h h h h h h h h h h h h h h h h h l h l h h h h h h h h h h h h h h h h h h h l h l h h h h h h h h h h h h h h h h h h h h h l h h l h h h h h h h h h h h h h h h h h h l h h l h h h h h h h h h h h h h h h h h h h h l h h h l h h h h h h h h h h h h h h h h h l h h h l h h h h h h h h h h h h h h h h h h h l h h h h l h h h h h h h h h h h h h h h h l h h h h l h h h h h h h h h h h h h h h h h h l h h h h h l h h h h h h h h h h h h h h h l h h h h h l h h h h h h h h h h h h h h h h h l h h h h h h l h h h h h h h h h h h h h h l h h h h h h l h h h h h h h h h h h h h h h h l h h h h h h h l h h h h h h h h h h h h h l h h h h h h h l h h h h h h h h h h h h h h h l h h h h h h h h l h h h h h h h h h h h h l h h h h h h h h l h h h h h h h h h h h h h h l h h h h h h h h h l h h h h h h h h h h h l h h h h h h h h h l h h h h h h h h h h h h h l h h h h h h h h h h l h h h h h h h h h h l h h h h h h h h h h l h h h h h h h h h h h h l h h h h h h h h h h h l h h h h h h h h h l h h h h h h h h h h h l h h h h h h h h h h h l h h h h h h h h h h h h l h h h h h h h h l h h h h h h h h h h h h l h h h h h h h h h h l h h h h h h h h h h h h h l h h h h h h h l h h h h h h h h h h h h h l h h h h h h h h h l h h h h h h h h h h h h h h l h h h h h h l h h h h h h h h h h h h h h l h h h h h h h h l h h h h h h h h h h h h h h h l h h h h h l h h h h h h h h h h h h h h h l h h h h h h h l h h h h h h h h h h h h h h h h l h h h h l h h h h h h h h h h h h h h h h l h h h h h h l h h h h h h h h h h h h h h h h h l h h h l h h h h h h h h h h h h h h h h h l h h h h h l h h h h h h h h h h h h h h h h h h l h h l h h h h h h h h h h h h h h h h h h l h h h h l h h h h h h h h h h h h h h h h h h h l h l h h h h h h h h h h h h h h h h h h h l h h h l h h h h h h h h h h h h h h h h h h h h l l h h h h h h h h h h h h h h h h h h h h l h h h l l h h h h h h h h h h h h h h h h h h h h l l h h h h h h h h h h h h h h h h h h h h h h l h l h h h h h h h h h h h h h h h h h h h l h l h h h h h h h h h h h h h h h h h h h h h l h h l h h h h h h h h h h h h h h h h h h l h h l h h h h h h h h h h h h h h h h h h h h l h h h l h h h h h h h h h h h h h h h h h l h h h l h h h h h h h h h h h h h h h h h h h l h h h h l h h h h h h h h h h h h h h h h l h h h h l h h h h h h h h h h h h h h h h h h l h h h h h l h h h h h h h h h h h h h h h l h h h h h l h h h h h h h h h h h h h h h h h l h h h h h h l h h h h h h h h h h h h h h l h h h h h h l h h h h h h h h h h h h h h h h l h h h h h h h l h h h h h h h h h h h h h l h h h h h h h l h h h h h h h h h h h h h h h l h h h h h h h h l h h h h h h h h h h h h l h h h h h h h h l h h h h h h h h h h h h h h l h h h h h h h h h l h h h h h h h h h h h l h h h h h h h h h l h h h h h h h h h h h h h l h h h h h h h h h h l h h h h h h h h h h l h h h h h h h h h h l h h h h h h h h h h h h l h h h h h h h h h h h l h h h h h h h h h l h h h h h h h h h h h l h h h h h h h h h h h l h h h h h h h h h h h h l h h h h h h h h l h h h h h h h h h h h h l h h h h h h h h h h l h h h h h h h h h h h h h l h h h h h h h l h h h h h h h h h h h h h l h h h h h h h h h l h h h h h h h h h h h h h h l h h h h h h l h h h h h h h h h h h h h h l h h h h h h ras a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 ba 0 ba 1 ba 2 dm 0 dm 1 dm 2 dm 3 clk clk we dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 dq 8 dq 9 dq 10 dq 11 dq 12 dq 13 dq 14 dq 15 dq 16 dq 17 dq 18 dq 19 dq 20 dq 21 dq 22 dq 23 dq 24 dq 25 dq 26 dq 27 dq 28 dq 29 dq 30 dq 31 dqs 0 dqs 1 dqs 2 dqs 3 0 = input low, 1 = input high, l = output low, h = output high
55 MB81N643289-50/-60 preliminary (ae1e) ac specification timing diagrams parameter description minimum maximum units t ts test mode entry set up time 10 ns t th test mode entry hold time 10 ns t epd test mode exit to power on sequence delay time 10 ns t tlz test mode output in low-z time 0 ns t thz test mode output in high-z time 0 20 ns t tca test mode access time from control signals (output enable & chip select) 40ns t tia test mode input access time 20 ns t toh test mode output hold time 0 ns t etd test mode entry to test delay time 10 ns t tih test mode input hold time 30 ns timing diagram C 1 : power-up timing diagram v dd cs pd cas *3 100 m s pause time test mode entry point notes: *1. scitt is enabled if cs = l, pd = l, cas = l at just power on. *2. all output buffers maintains in high-z state regardless of the state of control signals as long as the above timing is maintained. *3. cas must not be brought from high to low. *2 *1
56 MB81N643289-50/-60 preliminary (ae1e) timing diagram C 2 : scitt test entry and exit *1 t ts v cc cas cs pd t th entry exit pause 100 m s l l next power on sequence and normal operation h ? l notes: *1. if entry and exit operation have not been done correctly, cas , cs , pd pins will have some problems. *2. pc or pca commands must not be asserted. test mode is disable by those commands. *3. outputs must be disabled by cs = h or pd = l before exit. *2 *3 test mode t epd
57 MB81N643289-50/-60 preliminary (ae1e) timing diagram C 3 : output control (1) v dd cas cs pd t tlz entry dq turn to low-z at cs =l and pd =h dq 0 to dq 31 dqs 0 to dqs 3 t thz dq turn to high-z at cs =h cas must not brought from high to low high-z high-z high-z low-z time (a) time (b) time (c) memory device output buffer status this is not bus line level timing diagram C 4 : output control (2) v dd cas cs pd t tlz entry dq turn to low-z at cs =l and pd =h dq 0 to dq 31 dqs 0 to dqs 3 t thz cas must not brought from high to low high-z high-z high-z low-z time (a) time (b) time (c) memory device output buffer status this is not bus line level dq turn to high-z at pd =l
58 MB81N643289-50/-60 preliminary (ae1e) timing diagram C 5 : test timing (1) cs pd t etd test mode entry command test mode entry dq becomes low-z at cs =l and pd =h t tca t tia t tia t tia t tlz t toh t toh valid valid valid a 0 a 1 a 2 dq 0 to dq 31 dqs 0 to dqs 3 under check pins under test cas
59 MB81N643289-50/-60 preliminary (ae1e) timing diagram C 6 : test timing (2) cs -#1 pd test mode entry t tia t toh valid a 0 a 1 a 2 dq 0 to dq 31 dqs 0 to dqs 3 under check pins test mode exit under test cas cs -#2 valid valid valid valid t tia t tia t toh t thz t tlz t tia t tca t tih t tia t toh t tih t tih tested #1 device tested #2 device changed under test devices l l h
60 MB81N643289-50/-60 preliminary (ae1e) timing diagram C 7 : test timing (3) cs -#1 pd test mode entry t tia t toh valid a 0 a 1 a 2 dq 0 to dq 31 dqs 0 to dqs 3 under check pins test mode exit under test cas cs -#2 valid valid valid valid t tia t tia t toh t thz t tlz t tia t tca t tih t tia t toh t tih t tih tested #1 device tested #2 device changed under test devices l l h
61 MB81N643289-50/-60 preliminary (ae1e) n package dimensions c 1996 fujitsu limited f86001s-1c-1 0.45/0.75 (.018/.030) 0~8? 0.25(.010) details of "a" part 86 44 43 1 lead no. index .009 .002 +.002 0.04 +0.05 0.22 m 0.10(.004) 22.22 0.10(.875 .004) * 0.50(.020)typ 0.10(.004) 21.00(.827)ref 0.10 0.05 (.004 .002) (stand off) 1.20(.047)max .006 .001 +.002 0.03 +0.05 0.145 10.16 0.10(.400 .004) 11.76 0.20(.463 .008) "a" dimensions in mm (inches) (mounting height) 86-pin plastic tsop (ii) (fpt-86p-m01)
62 MB81N643289-50/-60 preliminary (ae1e) memo
63 MB81N643289-50/-60 preliminary (ae1e) memo
64 MB81N643289-50/-60 preliminary (ae1e) fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-8588, japan tel: (044) 754-3753 fax: (044) 754-3332 north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, u.s.a. tel: (408) 922-9000 fax: (408) 432-9044/9045 europe fujitsu mikroelektronik gmbh am siebenstein 6-10 63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 asia pacific fujitsu microelectronics asia pte. limited #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 f0003 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applica- tions, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume respon- sibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and office equipment industrial, communications, and measurement equipment, personal or household devices, etc.). important note: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high lives of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. there is a slight risk of failure with all semiconductor devices. you must protect against injury, damage to loss from such failures by incorporating safety design measures into your facility and equipment such as redun- dancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if the products described in this document represent goods or technologies subject to restrictions based on the foreign exchange and foreign trade control low, you must obtain permission to export these products.

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